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Sr.
ASIC Design Engineer, Emilia Romagna Client: Location: Job Category: Other
EU work permit required: Yes
Job Reference: 509040740686154956833710
Job Views: 4
Posted: 11.03.2025
Expiry Date: 25.04.2025
Job Description: We're growing!
Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer.

Responsibilities: Developing micro-architecture specifications for a next generation Computer Vision processor; Designing and implementing video compression logic, image processing logic, and computer vision processors in Verilog and SystemVerilog; Design integration, logic synthesis, and design optimization for timing,



area and power; Developing front-end methodologies and tool flows; Participating in chip bring-up and testing; Requirements: Master's degree in Electrical Engineering with 0-4 years of experience; Very good understanding of Computer architecture, Microprocessor, Digital electronics, VLSI/ASIC design, and Logic design; Good knowledge and experience in using hardware description languages, like Verilog/SystemVerilog; Ability to program in scripting languages, like Python and Perl; Knowledge of design verification, and functional coverage; Strong communication skills and a good team player; Knowledge in logic synthesis and timing closure are must, and some experience is a plus; Knowledge and/or experience in the areas of Image/Video processing, computer vision, machine learning are plus; To apply, please submit your resume with the subject: JOB#VLSI to (emailprotected) or apply online on the Ambarella website.

As an Equal Opportunity/Affirmative Action Employer, Vislab and Ambarella recruit qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status.

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